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蜂鸟开发板FPGA编译的问题

发表于开源蜂鸟E203 2020-04-06 13:27:07

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文件 mcs 步骤创建

Hi 各位，我在尝试使用Vivado 2018.2编译E203的mcs文件，遇到如下两个问题：

1. 按照书中步骤运行，执行完make mcs之后得到的mcs文件与git中预编译出来的mcs文件有几个字节的差异，这个有没有问题？会不会是因为版本的不同导致的结果差异？

2. 我想在Vivado创建一个项目，根据Makefile中的步骤创建了项目，但是项目的前面步骤都对了，就是在最后生成bitstream的步骤出错，说是有的管脚没有定义。

哪位高手能够帮忙看看这个项目需要怎么修改一下？多谢！！！

文件在百度盘：

旧项目 https://pan.baidu.com/s/18Rk3pZR97KUjwnWtkjM13w 提取码：tex1

新项目 https://pan.baidu.com/s/11KzsG3HriFH82Jyb8xgdjw 提取码：fefr

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用户评论 (19)

2020-04-08 14:19:32 领主文 1#

wujiboy：
多谢！已经解决。我重新建一个帖子来说明。另外，如果这个Vivado项目能够搞定就更好了，我想学习一下使用vivado图形版

嗯嗯，好的，我也来学习一下

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2020-04-07 23:07:49 wujiboy 2#

领主文：
这个e203是用控制台调用vivado实现生成mcs的，先确认一下哈，按照教程在控制台生成mcs没有问题吧

多谢！已经解决。我重新建一个帖子来说明。另外，如果这个Vivado项目能够搞定就更好了，我想学习一下使用vivado图形版

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2020-04-07 23:05:35 wujiboy 3#

领主文：
这个e203是用控制台调用vivado实现生成mcs的，先确认一下哈，按照教程在控制台生成mcs没有问题吧

直接在控制台生成mcs是可以的，不过缺省的board.tcl中定义的是75t可能需要修改一下。我修改成了100t正在执行 make mcs，重新生成system.mcs之后写入开发板，然后下载什么的都对了。原来出厂的时候那个开发板中竟然没有写入e203核？！！！！啊啊啊啊！！！

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2020-04-07 22:39:58 领主文 4#

wujiboy：
最新的项目文件在这里： https://pan.baidu.com/s/11KzsG3HriFH82Jyb8xgdjw 提取码：fefr 还是不成功，我修改成了100t，把mmcm, sys_reset也都改成最新的。生成bit stream还是出错： ERROR: [DRC NSTD-1] Unspecified I/O Standard: 235 out of 235 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hfextclk, hfxoscen, io_pads_aon_erst_n_i_ival, io_pads_aon_pmu_dwakeup_n_i_ival, io_pads_aon_pmu_padrst_o_oval, io_pads_aon_pmu_vddpaden_o_oval, io_pads_bootrom_n_i_ival, io_pads_dbgmode0_n_i_ival, io_pads_dbgmode1_n_i_ival, io_pads_dbgmode2_n_i_ival, io_pads_gpio_0_i_ival, io_pads_gpio_0_o_ds, io_pads_gpio_0_o_ie, io_pads_gpio_0_o_oe, io_pads_gpio_0_o_oval... and (the first 15 of 235 listed). ERROR: [DRC UCIO-1] Unconstrained Logical Port: 235 out of 235 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hfextclk, hfxoscen, io_pads_aon_erst_n_i_ival, io_pads_aon_pmu_dwakeup_n_i_ival, io_pads_aon_pmu_padrst_o_oval, io_pads_aon_pmu_vddpaden_o_oval, io_pads_bootrom_n_i_ival, io_pads_dbgmode0_n_i_ival, io_pads_dbgmode1_n_i_ival, io_pads_dbgmode2_n_i_ival, io_pads_gpio_0_i_ival, io_pads_gpio_0_o_ds, io_pads_gpio_0_o_ie, io_pads_gpio_0_o_oe, io_pads_gpio_0_o_oval... and (the first 15 of 235 listed).

这个e203是用控制台调用vivado实现生成mcs的，先确认一下哈，按照教程在控制台生成mcs没有问题吧

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2020-04-07 22:16:58 wujiboy 5#

领主文：
楼主改成100t可以试一下嘛

最新的项目文件在这里： https://pan.baidu.com/s/11KzsG3HriFH82Jyb8xgdjw 提取码：fefr 还是不成功，我修改成了100t，把mmcm, sys_reset也都改成最新的。生成bit stream还是出错： ERROR: [DRC NSTD-1] Unspecified I/O Standard: 235 out of 235 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hfextclk, hfxoscen, io_pads_aon_erst_n_i_ival, io_pads_aon_pmu_dwakeup_n_i_ival, io_pads_aon_pmu_padrst_o_oval, io_pads_aon_pmu_vddpaden_o_oval, io_pads_bootrom_n_i_ival, io_pads_dbgmode0_n_i_ival, io_pads_dbgmode1_n_i_ival, io_pads_dbgmode2_n_i_ival, io_pads_gpio_0_i_ival, io_pads_gpio_0_o_ds, io_pads_gpio_0_o_ie, io_pads_gpio_0_o_oe, io_pads_gpio_0_o_oval... and (the first 15 of 235 listed). ERROR: [DRC UCIO-1] Unconstrained Logical Port: 235 out of 235 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hfextclk, hfxoscen, io_pads_aon_erst_n_i_ival, io_pads_aon_pmu_dwakeup_n_i_ival, io_pads_aon_pmu_padrst_o_oval, io_pads_aon_pmu_vddpaden_o_oval, io_pads_bootrom_n_i_ival, io_pads_dbgmode0_n_i_ival, io_pads_dbgmode1_n_i_ival, io_pads_dbgmode2_n_i_ival, io_pads_gpio_0_i_ival, io_pads_gpio_0_o_ds, io_pads_gpio_0_o_ie, io_pads_gpio_0_o_oe, io_pads_gpio_0_o_oval... and (the first 15 of 235 listed).

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2020-04-07 21:17:14 wujiboy 6#

领主文：
楼主改成100t可以试一下嘛

正在尝试。改成100t还有一些需要重新做：IP中的mmcm, reset_sys需要重新生成。还有git的fpga目录的makefile也需要重新编写，修改型号从75t改成100t。所以我觉得现在git中预编译的system.mcs说不定也无法适应新的hbird评估板，我使用预编译的烧进去还是不对。

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2020-04-07 20:51:17 领主文 7#

楼主改成100t可以试一下嘛

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2020-04-07 20:24:15 领主文 8#

：

估计写文档的时候是用的75t

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2020-04-07 19:53:39 wujiboy 9#

领主文：
楼主的板子是75t的吗，我看你工程里好像选的是75t的，我这里是100t的芯片，我就先直接用100t试一下了，等编译一下看看情况

指的是FPGA型号？我的应该是100t的：板子是蜂鸟评估板，上面的FPGA是Artix-7XC7A100T

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2020-04-07 19:46:06 领主文 10#

楼主的板子是75t的吗，我看你工程里好像选的是75t的，我这里是100t的芯片，我就先直接用100t试一下了，等编译一下看看情况

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2020-04-07 19:05:23 领主文 11#

wujiboy：
链接：https://pan.baidu.com/s/18Rk3pZR97KUjwnWtkjM13w 提取码：tex1

收到，我看一下哈

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2020-04-07 17:31:41 wujiboy 12#

领主文：
好的，晚上来研究一下。

链接：https://pan.baidu.com/s/18Rk3pZR97KUjwnWtkjM13w 提取码：tex1

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2020-04-07 11:25:52 领主文 13#

wujiboy：
家里机器中有，晚上回去重新上传并同时放到百度盘共享中，文件不大只有600多K

好的，晚上来研究一下。

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2020-04-07 11:21:10 wujiboy 14#

领主文：
这个第二个问题工程文件有些问题，下载不下来，楼主可以考虑重新上传或者其他分享方式么？

家里机器中有，晚上回去重新上传并同时放到百度盘共享中，文件不大只有600多K

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2020-04-07 11:08:47 领主文 15#

这个第二个问题工程文件有些问题，下载不下来，楼主可以考虑重新上传或者其他分享方式么？

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